DRAMSys – The future of memory system optimization

Optimize your memory systems with DRAMSys: The powerful simulation framework for all product developments with DRAM

DRAMSys is the essential tool for developers and engineers who need full visibility into their product development with integrated DRAM subsystems. This advanced Open Source simulation framework is based on the SystemC TLM-2.0 standard and offers unprecedented flexibility and speed.

With DRAMSys you can easily master the challenges of modern memory systems. From analyzing power consumption to examining temperature distributions to identifying and correcting retention errors - DRAMSys offers you the options to optimally design your system.

What DRAMSys can do for you:

Best-in-class simulation models: Benefit from precise models that accurately represent the functionality, performance and temperature of DRAMs. Find the limiting factors in your system and make informed decisions.

DRAMSys Screenshot Trace Analyzer Metrics, Fraunhofer IESE
© Fraunhofer IESE

Intuitive Trace Analyzer: With the user-friendly trace analyzer tool you can gain deep insights into the behavior of your application. Examine bank parallelism, bus utilization and much more. With the Python interface you can calculate and visualize metrics such as access latency, bandwidth and accesses per activate.

Thermal analysis: Use DRAMSys in combination with tools like DRAMPower and 3D-ICE to perform thermal simulations. Optimize your refresh strategies and reach new levels of efficiency.

DRAMSys Screenshot Temperaturanalyse, Fraunhofer IESE
© DRAMSys thermal analyses, Fraunhofer IESE

The most important features of DRAMSys:

  • TLM2.0-AT-konform
  • Comprehensive DRAM support according to all current JEDEC standards: DDR3/4/5, LPDDR4/5, Wide I/O 1/2, GDDR5/5X/6/7, HBM2/3 with 100% accuracy. Other standards such as CXL, UCIe, DDR6 or HBM4 are in development
  • Flexible policies: Use various scheduling policies (FIFO, FR-FCFS and FR-FCFS with read/write grouping) and page policies (open, closed, open adaptive and closed adaptive) as well as power-down strategies to optimize the behavior of your memory architecture.
  • Detailed performance analysis: Estimate power consumption and perform thermal simulations.
  • Analysis of different refresh strategies (all-bank refresh, per-bank refresh, pulled-in, postpone) and power-down strategies (PDNA, PDNP, SREF, ...)
  • Visual result analysis: With the Trace Analyzer you receive immediate visual feedback and can base your decisions on well-founded data.
  • Full integration into the gem5 overall system simulation environment for integrated tests of individual software applications in the intended system and processor platform

Replace assumptions with solid facts and analysis.

With DRAMSys4.0, you have the power to systematically explore your design space and find the optimal DRAM architecture for your specific requirements. Whether you want to test new standards such as DDR5 or LPDDR5, configure the memory controller or optimize your system application, DRAMSys gives you the precise insights you need to be successful.

The application cases are diverse:

  • Which DRAM configuration or standard is best for my product: DDR5, LPDDR5, HBM3?
  • How will new standards like DDR5 or LPDDR5 change the behavior of my system? Will they provide greater value to my system?
  • How can I configure the memory controller to achieve maximum performance or minimum power consumption?
  • How can I optimize my system application with respect to the DRAM subsystem used?

DRAMSys is the fastest and most accurate simulation framework compared to other DRAM simulators. You can achieve

  • maximized performance by identifying and eliminating memory bottlenecks
  • reduced costs by optimizing expenses with accurate forecasts
  • increased flexibility by testing different scenarios for optimal memory configuration

and benefit from a shorter time to market compared to using traditional RTL modelers.

Take your project to the next level. Schedule a meeting and find out for yourself how simulation-based facts can revolutionize your development.

Grafik
© Fraunhofer IESE

Introductory lecture on DRAMSYs

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Autoren: Lukas Steiner, Matthias Jung, Fe­lipe Salerno Prado, Kir­ill Bykov and Nor­bert Wehn

Lukas Steiner explains the basics of DRAMSys at the SAMOS 2020 conference. He discusses the special TLM2.0 technology and explains the advantages of DRAMSys compared to conventional simulators.

Reference

Mercedes-Benz AG

 

The amount of data that needs to be processed in real time in today's vehicles is constantly increasing. At the same time, there are requirements for low power consumption and great cost pressure, which is leading to the increased use of components that were originally developed for the consumer market. 

 

Together with the Technical University of Kaiserslautern, Fraunhofer IESE has developed a measurement platform (DRAMMeasure) for DRAM memory for Mercedes-Benz AG in order to determine performance parameters for future control units.

DRAMsys – Cycle-Accurate Simulation using Transactions

DRAMsys is a simulator for modern RAM systems, built by researchers at Fraunhofer IESE and the Technische Universität Kaiserslautern

Arteris

Combining FlexNoC and Ncore from Arteris with Fraunhofer IESE DRAMSys4.0 enables customers to improve performance, reduce cost and accelerate the advanced DRAM-centric SoC development schedules

 

HiPEAC Tech Transfer Award Highlights DRAMSys4.0 Collaboration

More information about DRAMSys

Software

Open-source Version

Die Open-Source-Version von DRAMSys wird auf github gehostet. Das Repository wird regelmäßig mit neuen Funktionen aktualisiert.

Research project

MEMTONOMY-2

New storage systems for autonomous driving 

Research project

DI-DERAMSys

Designinitiative Mikroelektronik: Research in the field of design tools for sovereign chip development with open source (DE:Sign).

ATZ elektronik 11|2020

Modern memory architectures

Semiconductor memories such as DRAMs or flash are an aspect that often receives little attention, but which will become a limiting factor in future vehicle architectures.

Video

Temperature analysis 

Temperature measurement of a smartphone with Wide I/O DRAM and use of DRAMSys to investigate different refresh strategies.

Research project

MEMTONOMY

Optimization of working memory for driver assistance systems and autonomous driving. Fraunhofer wants to close the research gap with the participation of Bosch and TU Kaiserslautern.

    • PIMSys: A Virtual Prototype for Processing in Memory
      D. Christ, L. Steiner, N. Wehn, M. Jung. 10th International Symposium on Memory Systems (MEMSYS 2024), October, 2024, Washington, DC, USA.

    • A Novel System Simulation Framework for HBM2 FPGA Platforms
      H. G. M. Hernandez, V. Iskandar, L. Steiner, P. Holzinger, M. Jung, D. Goehringer, M. Huebner, N. Wehn and M. Reichenbach Springer LNCS International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS)., July, 2024, Samos Island, Greece.

    • A Precise Measurement Platform for LPDDR4 Memories
      J. Feldmann, L. Steiner, D. Christ, T.Psota, M. Jung, and N. Wehn. ACM International Symposium on Memory Systems (MEMSYS 2023)

    • Automatic DRAM Subsystem Configuration with irace
      L. Steiner, G. Delazeri, I. Prando Da Silva, M. Jung and N. Wehn. International Conference on High-Performance and Embedded Architectures and Compilers 2020 (HiPEAC), Workshop on: Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO), January, 2023, Toulouse, France

    • A Framework for Formal Verification of DRAM Controllers (DOI, Arxiv)
      L. Steiner, C. Sudarshan, M. Jung, D. Stoffel and N. Wehn. ACM/IEEE International Symposium on Memory Systems (MEMSYS 2022), October, 2022, Washington, DC, USA

    • Unveiling the Real Performance of LPDDR5 Memories (DOI, Arxiv)
      L. Steiner, M. Jung, M. Huonker and N. Wehn. ACM/IEEE International Symposium on Memory Systems (MEMSYS 2022), October, 2022, Washington, DC, USA

    • DRAMSys4.0: An Open-Source Simulation Framework for In-Depth DRAM Analyses (DOI/PDF)
      L. Steiner, M. Jung, F. S. Prado, K. Bykov, N. Wehn Springer,
      International Journal of Parallel Programming (IJPP)
      , 2022

Are you interested in operating the simulation framework?

 

Contact us!!

 

We would be happy to discuss your requirements over the phone or by appointment.

Are you interested in:

  • the latest JEDEC standards?
  • the Trace Analyzer?
  • support for setting up DRAMSys?
  • customized modifications?
  • DRAM consulting?